1. Field of the Invention
The invention relates to a bias driving technique for a flat panel display. More particularly, the invention relates to a driving technique for dynamic bias for controlling a buffer to operate in a low bias state during a power-saving period, so as to maintain a display quality and reduce power consumption.
2. Description of Related Art
Buffers are widely applied in various electronic devices, and especially in a flat panel display (for example, a liquid crystal display (LCD)), a large amount of the buffers has to be used for driving pixel loads (taking the LCD as an example, the pixel load refers to a pixel capacitor). In detail, a source driver of the flat panel display requires a large amount of the buffers, which can transmit data voltage of each pixel to the corresponding pixel load, so as to update each pixel data of a frame.
In a conventional bias control technique of the buffer, the flat panel display provides adequate bias to each buffer, so that each buffer has adequate driving capability to quickly update the data voltage of the pixel load, as that shown in FIG. 1 and FIG. 2. FIG. 1 is a block diagram illustrating a conventional flat panel display 10, and FIG. 2 is a bias waveform diagram of a buffer 140 used for driving a pixel load 180. Referring to FIG. 1, the flat panel display 10 mainly includes a timing controller 110, a source driver 120, a gate driver 150 and a display panel 160. The source driver 120 includes a driving circuit 130 and a plurality of buffers 140, wherein a number of the buffers 140 is determined according to a number of pixels on each scan line in the display panel 160. A pixel circuit 165 in the display panel 160 is taken as an example, and the pixel circuit 165 includes a switch 170 and a pixel load 180.
In the present embodiment, the timing controller 110 receives a data signal D to be displayed on the display panel 160 and a data enable signal DE, and converts the received signals into a line latch signal TP, and an output enable signal OE, etc., and respectively provides the converted signals to the source driver 120 and the gate driver 150 for utilization. In the present embodiment, the data signal D includes a plurality of data voltages DV corresponding to each of the pixels. The gate driver 150 receives the output enable signal OE, and generates a switch control signal GL according to the output enable signal OE, so that the data voltage DV can be transmitted to the pixel load 180 through the switch 170. The driving circuit 130 receives the data signal D, and transmits the data voltage DV corresponding to the pixel circuit 165 to the buffer 140 according to the line latch signal TP. In this way, the buffer 140 receives adequate bias all the time, and transmits the data voltage DV to one end of the switch 170 of the pixel circuit 165, and further transmits the data voltage DV to the pixel load 180 according to the switch control signal GL received by a control end of the switch 170, and a detailed waveform diagram thereof is as that shown in FIG. 2.
Referring to FIG. 2, the line latch signal TP triggers the driving circuit 130 to update the data voltage DV. After the line latch signal TP generates a pulse, the buffer 140 adjusts a data voltage OPD at an output terminal of the buffer 140 according to the received data voltage DV during a transition period T1, so as to provide the data voltage DV to one end of the switch 170. Then, during a conduction period (i.e. a period that the switch control signal GL is in a high level) of the switch 170, the data voltage OPD is supplied to the pixel load 180 through the switch 170, so that the display panel 160 can display an image provided by the data signal D.
Since the conventional flat panel display 10 provides the same and adequate bias to each of the buffers 140, though the buffer 140 does not require such powerful driving capability for the data voltage OPD during a period other than an output transition period (for example, the transition period T1 shown in FIG. 2), so that extra power is wasted in the buffer 140, which causes a waste of energy. However, if the bias of the buffer 140 is reduced, the driving capability for the data voltage DV is inadequate, so that the data voltage DV cannot be transmitted to the pixel load 180 in time, which may cause a partial white phenomenon and a discontinuous phenomenon of the image displayed on the display panel 160.